1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a dynamic semiconductor memory device having a sense amplifier differentially amplifying memory cell data. More specifically, the present invention relates to the structure of a drive part for the sense amplifier.
2. Description of the Background Art
Following the recent development and spread of computers and information processing terminals, requirement for devices employed as main storage in these equipments is increasingly severe. With respect to a DRAM (dynamic random access memory) most widely utilized as the main storage, a DRAM capable of transferring data at a high speed such as an SDRAM (synchronous DRAM) inputting/outputting data in synchronization with a clock signal or a DDR (double data rate) SDRAM inputting/outputting data in synchronization with both leading and trailing edges of a clock signal is now in the process of popularization.
The DRAM stores information in a capacitor of a memory cell in the form of charges. High-level data written in a DRAM cell is spontaneously disappears due to a leakage current when left intact, and must be periodically restored through an operation referred to as refresh.
The specification for a recent DRAM defines an operation referred to as self-refresh. In such a self-refresh operation mode, a timer in the DRAM automatically sets a refresh timing for automatically performing the refresh operation.
The self-refresh operation is performed in a standby state when no access is made to DRAM. Therefore, a continuous wait time in a portable communication information terminal, for example, can be increased by suppressing a self-refresh current consumed in the self-refresh operation (since the life time of a battery can be prolonged).
Among components of the self-refresh current, what accounts for the largest percentage is a current for reading data stored in a memory cell and rewriting the data, i.e., the so-called sense current Issr. This sense current is now described.
FIG. 27 illustrates the structure of a memory cell array of a conventional DRAM. Referring to FIG. 27, the DRAM includes memory cells MC arranged in a matrix of rows and columns, a pair of bit lines BL and /BL arranged in correspondence to each column of the memory cells and a word line WL arranged in correspondence to each row of the memory cells MC. FIG. 27 representatively shows a single memory cell MC. Memory cell MC includes a memory cell capacitor Cs for storing information and an access transistor MT formed by an n-channel MOS transistor and rendered conductive in response to the signal voltage on word line WL for connecting the memory cell capacitor Cs with bit line BL. Bit lines BL and /BL have parasitic capacitances Cb respectively.
A bit line equalize/precharge circuit E/P precharging and equalizing the bit lines BL and /BL to an intermediate voltage Vble in response to a bit line equalization instruction signal BLEQ and a sense amplifier circuit S/A differentially amplifying the voltages of bit lines BL and /BL in response to sense amplifier activation signals SON and ZSOP are provided for bit lines BL and /BL.
Bit line equalize/precharge circuit E/P includes precharge transistors Q7 and Q8 transmitting the intermediate voltage Vble to bit lines BL and /BL respectively in response to bit line equalization instruction signal BLEQ and an equalize transistor Q9 shorting the bit lines BL and /BL in response to bit line equalization instruction signal BLEQ. The transistors Q7 to Q9 are formed by n-channel MOS transistors (insulated gate field effect transistors).
Sense amplifier circuit S/A includes an N sense amplifier activated in activation of the sense amplifier activation signal SON for discharging one of bit lines BL and /BL at a lower potential and a P sense amplifier activated in activation of the sense amplifier activation signal ZSOP for charging one of bit lines BL and /BL at a higher potential. N sense amplifier includes an n-channel MOS transistor Q1 having a drain connected to bit line BL and a gate connected to bit line /BL, an n-channel MOS transistor Q2 having a drain connected to bit line /BL and a gate connected to bit line BL and an n-channel MOS transistor Q3 rendered conductive in activation of sense amplifier activation signal SON for transmitting a sense power supply voltage Vsan to sources of the MOS transistors Q1 and Q2. The sense power supply voltage Vsan is generally at the level of a ground voltage Vsg.
P sense amplifier includes a p-channel MOS transistor Q4 having a drain connected to bit line BL and a gate connected to bit line /BL, a p-channel MOS transistor Q5 having a drain connected to bit line /BL and a gate connected to bit line BL and a p-channel MOS transistor Q6 rendered conductive in activation of sense amplifier activation signal ZSOP for transmitting a sense power supply voltage Vsap to sources of the MOS transistors Q4 and Q5. Sense power supply voltage Vsap is generally at the level of a power supply voltage Vdds. A refresh operation for memory cell MC will be now described with reference to a signal waveform diagram shown in FIG. 28.
In a standby state, sense amplifier activation signal SON is low at the ground voltage Vss, sense amplifier activation signal ZSOP is inactive at the power supply voltage Vdds, and sense amplifier circuit S/A is inactive. Bit line equalization instruction signal BLEQ is in a high-level active state, and all MOS transistors Q7 to Q9 included in bit line equalize/precharge circuit E/P are rendered conductive so that bit lines BL and /BL are precharged and equalized to the level of intermediate voltage Vble. The intermediate voltage Vble is generally at a level of half the power supply voltage Vdds (=Vdds/2). Word line WL is at the level of ground voltage Vsg, and access transistor MT of memory cell MC remains non-conductive.
When a memory cycle is started, bit line equalization instruction signal BLEQ falls to a low level, bit line equalize/precharge circuit E/P is inactivated and bit lines BL and /BL enter electrically floating states at the level of intermediate voltage Vble.
Then, a row selection circuit (not shown) drives the word line WL to a selected state in accordance with an address signal, and the voltage level of word line WL increases. When the voltage level of word line WL exceeds the gate-to-source voltage of access transistor MT by a level corresponding to the threshold voltage of the access transistor, access transistor MT starts conducting, and electric charges move between bit line BL and memory capacitor Cs. Referring to FIG. 28, the memory cell MC stores high-level data and the voltage level of bit line BL increases.
Bit line /BL connected with no memory cell remains at the level of intermediate voltage Vble.
When the voltage difference between bit lines BL and /BL is sufficiently enlarged, sense amplifier activation signals SON and ZSOP are activated. When sense amplifier activation signal SON is activated to go high, MOS transistor Q3 is rendered conductive in sense amplifier circuit S/A to transmit the sense power supply voltage Vsan to the sources of MOS transistors Q1 and Q2. Responsively, N sense amplifier is activated and bit line /BL at a lower potential is discharged to the level of sense power supply voltage Vsan (=Vsg). When sense amplifier activation signal ZSOP is activated to go low, MOS transistor Q6 is rendered conductive in sense amplifier circuit S/A to transmit the sense power supply voltage Vsap to the sources of MOS transistors Q4 and Q5, and P sense amplifier is activated. P sense amplifier charges the bit line BL at a higher potential to sense power supply voltage Vsap (=Vdds).
Word line WL is at the level of a voltage Vpp higher than power supply voltage Vdds. Therefore, the high-level data at the level of power supply voltage Vdds on bit line BL is transmitted to memory cell capacitor Cs with no influence by threshold voltage loss across access transistor MT. Thus, the high-level data is completely rewritten and refreshed in memory cell MC. If memory cell MC stores low-level data, a voltage at the level of sense power supply voltage Vsan is transmitted to memory cell capacitor Cs for similarly refreshing the data.
When the refresh cycle is completed, word line WL is driven to a non-selected state and then sense amplifier activation signals SON and ZSOP are sequentially inactivated. Thus, the refreshed data is stored in memory cell MC. Then, bit line equalization instruction signal BLEQ goes high, bit line equalize/precharge circuit E/P is activated, and the bit line voltages at the levels of power supply voltage Vdds and ground voltage Vsg are precharged and equalized to the level of intermediate voltage Vble.
The maximum amplitude dVbl of bit line BL is given as Vddsxe2x88x92Vble=Vdds/2. Bit line BL is charged by charges supplied from a sense power source. Assuming that Cb represents the bit line load and N represents the number of simultaneously refreshed pairs of bit lines, the quantity Qs of charges consumed in a single refresh operation is expressed as follows:
Qs=Nxc2x7Cbxc2x7dVbl
Assuming that Tref represents the period of the refresh operation, i.e., the refresh interval, the sense current Issr flowing in the self-refresh operation is expressed as follows:                                                                         Issr                =                                  Qs                  /                  Tref                                                                                                        =                                  A                  ·                                      dVb1                    /                    Tref                                                                                      ⁢                  
                ⁢                              where            ⁢                          xe2x80x83                        ⁢            A                    =                      N            ·            Cb                                              (        1        )            
In order to reduce the sense current Issr, the refresh interval Tref must be increased and the bit line amplitude dVbl must be reduced.
In order to increase the refresh interval Tref, it is important to implement a memory cell having a long data holding time. In order to implement such a memory cell, contrivance on circuit and layout is required in addition to improvement of characteristics on manufacturing process.
In order to reduce the bit line amplitude dVbl (=Vdds/2), the power supply voltage Vdds is generally reduced.
FIG. 29 illustrates an exemplary structure of a conventional sense power supply circuit. Referring to FIG. 29, the conventional sense power supply circuit includes a compare circuit CMP comparing a reference voltage Vrefs with a sense power supply voltage Vsap (=Vdds) and a drive transistor DR supplying a current to a sense power supply line from an external power supply node receiving an external power supply voltage ext. Vdd in accordance with an output signal of compare circuit CMP. Drive transistor DR is formed by a p-channel MOS transistor.
Compare circuit CMP includes n-channel MOS transistors Q10 and Q11 receiving the reference voltage Vrefs and the sense power supply voltage Vsap in respective gates, p-channel MOS transistors Q12 and Q13 supplying currents to MOS transistors Q10 and Q11 from the external power supply node, and an n-channel MOS transistor Q14 coupled between MOS transistors Q10 and Q11 and a ground node and rendered conductive in activation of a control signal VDCON for forming a path flowing an operating current for compare circuit CMP.
P-channel MOS transistor Q13 has a gate and a drain interconnected with each other as well as a gate connected to a gate of MOS transistor Q12. MOS transistors Q12 and Q13 form a current mirror circuit. An output signal of compare circuit CMP is output from a connection node between MOS transistors Q12 and Q10 and supplied to the gate of drive transistor DR.
The control signal VDCON is activated in activation of a sense amplifier circuit.
In the structure of the sense power supply circuit shown in FIG. 29, when the control signal VDCON is low, MOS transistor Q14 is rendered non-conductive, the output signal of compare circuit CMP is at the level of external power supply voltage ext. Vdd, drive transistor DR is rendered non-conductive, and current consumption in the sense power supply circuit is reduced.
When control signal VDCON is activated, compare circuit CMP compares the reference voltage Vrefs with the sense power supply voltage Vsap. When sense power supply voltage Vsap is higher than reference voltage Vrefs, the output signal of compare circuit CMP goes high, drive transistor DR remains non-conductive, and supply of a current to a sense power supply line is stopped.
When sense power supply voltage Vsap is reduced below the reference voltage Vrefs, the output signal of compare circuit CMP goes low in proportion to the difference between sense power supply voltage Vsap and reference voltage Vrefs, the conductance of drive transistor DR is increased, and a current is supplied to the sense power supply line from the external power supply node. Thus, the level of sense power supply voltage Vsap is increased.
The sense power supply circuit shown in FIG. 29 holds the sense power supply voltage Vsap substantially at the same level as the reference voltage Vrefs. The reference voltage Vrefs is held at a constant level lower than external power supply voltage ext. Vdd, thereby reducing the level of sense power supply voltage Vsap, so that the bit line amplitude dVbl as well as the charging current can be responsively reduced.
The sense power supply voltage Vsap determines the level of high-level data written in a memory cell. If the level of reference voltage Vrefs is reduced and responsively the level (Vdds) of sense power supply voltage Vsap is reduced, the quantity of charges stored in a memory cell capacitor is reduced and the data hold time is reduced for high-level data written in the memory cell. Therefore, the refresh interval Tref must be set short in order to hold the memory cell data, and there is a possibility that the sense current Issr is not reduced as a whole.
In order to solve the aforementioned problem, Asakura et al. has proposed a BSG (boosted sense ground) scheme. While the contents of the BSG scheme are described in detail in ISSCC Digest of Technical Papers 1994, pp. 1303 to 1309, for example, the principle of the BSG scheme is now briefly described with reference to FIG. 30.
FIG. 30 schematically illustrates the sectional structure of a memory cell MC. Referring to FIG. 30, memory cell MC includes high-concentration N-type impurity regions 502a and 502b formed spacedly on the surface of a P-type substrate 500, a conductive layer 504 formed on a channel region between the impurity regions 502a and 502b with a gate insulation film 503 underlaid, and an interlayer isolation film 505b. Conductive layer 504 forms a word line WL, and the conductive layer 505a forms a bit line BL.
Memory cell MC further includes a conductive layer 510 electrically connected with impurity region 502b through a contact hole formed in interlayer isolation film 505b and a conductive layer 514 arranged facing to the upper part of conductive layer 510. Conductive layer 514 has a V-shaped upper shape in sectional structure, and conductive layer 514 includes a projecting part 514 extending into the V-shaped portion on the upper region of conductive layer 510 through a capacitor insulation film 512. Conductive layer 510 serves as a conduction node between an access transistor MT and a memory cell capacitor Cs, i.e., a storage node SN. Memory cell capacitor Cs is formed on a region where conductive layers 510 and 514 face to each other through capacitor insulation film 512.
While memory cell MC has a stacked capacitor structure in FIG. 30, the stacked capacitor may have any other structure such as a cylindrical or fin structure or a T-shaped sectional structure.
Consider that word line WL is held at the level of a ground voltage GND, a bit line voltage Vbl is applied to bit line BL and a voltage Vch corresponding to high-level data is held in storage node SN in memory cell MC shown in FIG. 30. An intermediate voltage of a cell plate voltage Vcp (=Vdds/2) is applied to conductive layer 514 serving as a cell plate electrode layer CP.
Main leakage sources in memory cell MC are (1) a leakage current Ils to P-type substrate 500 through a p-n junction between impurity region 502b and the substrate 500 and (2) a leakage current Ilb toward bit line BL dependent on the subthreshold characteristic of the access transistor.
The level of the leakage current Ils to P-type substrate 500 so depends on a potential difference Vpn applied to the p-n junction between impurity region 502b and P-type substrate 500 that the leakage current Ils increases as the potential difference Vpn increases. Referring to FIG. 30, storage node SN is at the voltage Vch corresponding to high-level data and a bias voltage Vbb is applied to P-type substrate 500, and hence the potential difference Vpn is expressed as follows:
Vpn=Vchxe2x88x92Vbb
On the other hand, the leakage current Ilb flowing to bit line BL through the access transistor is expressed by the difference between a gate-to-source voltage Vgs and a threshold voltage Vth of the access transistor as follows:
Ilb=Ilb0xc2x710xcex9(Vgsxe2x88x92Vth)/Sxe2x80x83xe2x80x83(2)
where xcex9 represents an exponentiation. In the above equation (2), Ilb0 represents a current value defining the threshold voltage Vth, and S represents a coefficient decided according to the transistor structure and the manufacturing process and is expressed as dVgs/dlogId, where Id represents a drain current.
In the equation (2), it appears that the leakage current Ilb is not dependent on the potential Vbl of bit line BL connected with the access transistor. However, the threshold voltage Vth is dependent on the substrate-to-source voltage Vbs=Vbbxe2x88x92Vbl, where Vbb is non-positive, and reduces as the bit line voltage, or the source voltage Vbl reduces, i.e., the absolute value of the substrate-to-source voltage Vbs reduces.
When the bit line BL corresponding to a memory cell connected to a non-selected word line in a memory block to be refreshed swings in potential to low-level data (the bit line voltage Vbl is equal to ground voltage GND in the prior art), for example, the absolute value of the substrate-to-source voltage Vbs of the access transistor in the memory cell reduces, and the bit line leakage current Ilb increases even if the word line WL is at the level of ground voltage GND. As understood from the above equation (2), the bit line leakage current Ilb deviates by about 10 times if the threshold voltage Vth slightly changes by 0.1 V since an S factor is generally 0.1 V.
In order to suppress the aforementioned bit line leakage current, the bias voltage Vbb to P-type substrate 500 can be set negative as shown in FIG. 31A. Upon setting the substrate bias voltage Vbb deep in the negative direction, the bit line leakage current Ilb is suppressed. However, the potential difference applied across the p-n junction between impurity region 502b and P-type substrate 500 increases on the contrary, to increase the substrate leakage current Ils. Power supply voltage Vdds determines the level of the voltage Vch corresponding to high-level data of storage node SN, and when the substrate leakage current Ils increases due to the deep substrate bias voltage in the negative direction, it is difficult to hold the high-level data over a long period if the power supply voltage is lowered. On the other hand, the BSG scheme provides the following advantages:
(a) As shown in FIG. 31B, a back gate bias voltage is set at the level of the ground voltage GND while a positive voltage Vbsg is applied to the bit line BL (/BL). The word line WL is at the level of ground voltage GND in a non-selected state. Therefore, the gate-to-source voltage Vgs of access transistor MT is at a negative level xe2x88x92Vbsg. Ground voltage GND is applied to P-type substrate 500, and hence the potential difference Vpn applied across the p-n junction between impurity region 502b and P-type substrate 500 in the storage node is equal to the voltage Vch of the high-level data. Thus, the potential difference applied across the p-n junction can be reduced.
In other words, the gate-to-source voltage Vgs of access transistor MT can be rendered negative, the voltage Vbs applied across the p-n junction between source impurity region 502a of access transistor and P substrate 500 attains a reverse biasing state, and the bit line leakage current Ilb can be reduced without applying a negative voltage to P substrate 500.
(b) The potential difference Vpn applied across the p-n junction in storage node SN is reduced and the substrate leakage current Ils can be reduced.
(c) The precharge voltage Vble for the bit line BL must be half the bit line amplitude, and is Vdds/2+Vbsg/2. In sensing operation, the voltage level on bit line BL or /BL is sensed from the precharge voltage Vble to power supply voltage Vdds or to the voltage Vdsg, and hence the bit line amplitude dVbl can be reduced by Vbsg/2 and current consumption can be reduced.
The destruction rate of the high-level data is relaxed due to the aforementioned items (a) and (b) and hence the refresh interval Tref can responsively be made long. In other words, the power supply voltage Vdds can be lowered if the same refresh interval Tref is allowed. In this case, therefore, the bit line amplitude dVbl can be reduced by the above item (c), and the sense current Issr can be remarkably reduced in accordance with the above equation (1).
As described above, the BSG scheme has excellent advantages of reduction of the sense current and improvement of the refreshability. The bias voltage Vbb applied to the substrate region, i.e., the back gate of the access transistor is at the level of ground voltage GND, and no negative bias voltage need be applied and the circuit structure is simplified. However, the low-level voltage of the bit line BL is higher than the ground voltage GND by about 0.5 V. A bit line precharged to the intermediate voltage level must be discharged to be held at the level of the voltage Vbsg, and a circuit generating the bit line boosted source ground voltage Vbsg must have large current drivability (a large number of bit lines are simultaneously discharged and hence the bit line discharge current must be absorbed). Therefore, when utilizing diode-connected p-channel MOS transistors is utilized, for example, variation of threshold voltages or temperature dependency of the diode-connected transistors becomes a negligible factor and it is difficult to stably generate the bit line boosted source ground voltage Vbsg in a dc manner.
Immediately after sense amplifier circuit S/A is activated to start a sensing operation, charges abruptly flow into a sense low-level power supply line (Vbsg level) from the bit line having been precharged at level of intermediate voltage ((Vdds+Vbsg)/2) to raise the level of the voltage Vbsg transiently. When the level of the boosted source ground voltage Vbsg remarkably increases, the gate-to-source voltage of the n-channel MOS transistors (Q1 and Q2) included in N sense amplifier of sense amplifier circuit S/A reduces and the n-channel MOS transistors of the N sense amplifier enter OFF states, the bit line cannot be discharged and hence there is a possibility that the sensing operation remarkably is slowed down. In order to suppress such transient fluctuation of the boosted source ground voltage Vbsg, therefore, a circuit generating the boosted source ground voltage Vbsg must have extremely high current drivability and ability for stably holding the voltage level.
In addition, as another way to stabilize the boosted source ground voltage Vbsg, a stabilizing capacitor having a sufficiently large capacitance value should be connected to the sense low-level power supply line. When an NMOS capacitor employing an n-channel MOS transistor is utilized for minimizing the occupying area, however, the threshold voltage Vthn of the MOS transistor is substantially equal to the boosted source ground voltage Vbsg, and there is a possibility that a sufficient inversion layer is not formed in a channel region of the MOS capacitor, and the MOS capacitor becomes instable, and it may be impossible to implement a reliable stabilizing capacitor.
As shown in FIG. 32A, a ground voltage utilized for generating the boosted source ground voltage Vbsg and ground voltage GND applied to the P substrate as a bias voltage are of different systems. Thus, noise generated in the P substrate is prevented from exerting bad influence on boosted source ground voltage Vbsg.
In this case, however, the ground voltage GND applied to the P substrate as a bias voltage and the boosted source ground voltage Vbsg may fluctuate in different phases and amplitudes due to a noise, as shown in FIG. 32B. When the voltages Vbsg and GND change in the same phase and amplitude, conditions Vbs less than 0 and Vgs less than 0 simultaneously hold in the access transistor and increase of the bit line leakage current is suppressed.
If the noise of the P substrate and that of the boosted source ground voltage Vbsg are different in amplitude or phase from each other, however, the level of the bias voltage GND for the P substrate exceeds the boosted source ground voltage Vbsg in the worst case. In this case, the voltages Vbs and Vgs take positive values, the gate-to-source voltage Vgs of the access transistor reaches a positive level, the bit line leakage current Ilb abruptly increases and the refresh characteristic of the memory cell remarkably deteriorates.
While the aforementioned advantage of the BSG scheme in the above item (c), i.e., reduction of the bit line amplitude brings another advantage of reduction of the sense current, a problem may arise in terms of the sensing speed.
Consider that a read voltage xcex94V is transmitted to the bit line BL as shown in FIG. 33. In this state, the sense power supply voltages Vbsg and Vdds are supplied to sense amplifier circuit S/A. The gate-to-source voltages Vgs of MOS transistors Q1 and Q2 are substantially about (Vddsxe2x88x92Vbsg)/2 (read voltage xcex94V is neglected), and the gate-to-source voltages Vgs of MOS transistors Q4 and Q5 are also about (Vddsxe2x88x92Vbsg)/2. In this case, therefore, the gate-to-source voltages Vgs of MOS transistors Q1, Q2, Q4 and Q5 are substantially equal to the bit line amplitude dVbl. If the bit line amplitude dVbl reduces, therefore, the absolute values of the gate-to-source voltages Vgs of the MOS transistors included in sense amplifier circuit S/A reduce to reduce the ability of charging/discharging the bit lines BL and /BL. In this case, therefore, the timing at which the voltage levels of bit lines BL and /BL are made definite may be retarded to reduce the sensing speed.
The sensing operation itself remains identical between in a self-refresh operation and a normal operation mode for accessing data. If the sensing speed is slowed down due to reduction of the bit line amplitude, therefore, the sensing speed in the normal operation mode is also reduced, the timing for column selection must be retarded, and there is a possibility that the access time is increased in response.
An object of the present invention is to provide a semiconductor memory device which can be improved in refresh characteristics without increasing current consumption.
Another object of the present invention is to provide a semiconductor memory device which can stably supply a write voltage of a desired level to a bit line.
Still another object of the present invention is to provide a semiconductor memory device which can stably supply a sense power supply voltage of a desired level to a sense amplifier circuit.
A further object of the present invention is to provide an improved semiconductor memory device of a BSG scheme which can be improved in refresh characteristics without reducing a sensing speed.
Briefly stated, the semiconductor memory device according to the present invention includes a decoupling capacitor provided to a sense power supply line for stably generating a voltage written in a refresh memory cell, and generates the write voltage by capacitance division with a load capacitance of the sense amplifier circuit.
A sensing operation is basically an operation of charging/discharging a capacitive load determined by the capacitance of a memory cell and parasitic capacitances of a pair of bit lines. Therefore, stable voltage levels can be generated on the pair of bit lines by charge transfer by means of a capacitive element for enabling a stable sensing operation and preventing slow-down of the sensing operation. The voltage level of a bit line is determined by capacitance division of the capacitive element and a load of the bit line, and hence the bit line can be simply held at a desired voltage level for preventing deterioration of refresh characteristics.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.